Something about Fetch, Decode, Execute

[mike_g]

As theres quite a few people here that code in ASM here I'm hoping someone could answer this for me. In the FDE cycle, if the same instruction (involving data) has to be run several times does the processor have to fetch the instruction over and over before each time it can get the data. Or does it leave the instruction in its register and just fetch the data until a new instruction is needed. This would be better, but is it how it works?  Cheers.

[rain_storm]

if you use the same instruction (as in the exact same instruction which is the exact same address in memory) then that instruction is only fetched once then the CPU accesses the instruction in the cache that is until the cache has been filled. this will free up the data bus for better use

[mike_g]

I just realised that if the command was the same but a parameter that went with it was different, then it would not be exactly the same instruction. So I guess it would have to fetch the instruction every time. Cheers rain_storm.

[Jim]

Depends on the instruction cacheing on the chip.  IIRC, CPUs like Z80 don't have an instruction cache and have to re-read every instruction from RAM every time.  68000 (or was it MIPS4000?) has a 4 instruction cache so if there's a tight loop it might not have to re-fetch anything.  Newer Intel CPUs have 10s or 100s of instructions in local caches.

So the fetch decode execute cycle is about as simple as the CPU can be described, fetch the instruction, decode it (which might mean all sorts of things, like fetching data from RAM) and then execute the result (which might mean storing data back to RAM).  In a modern Intel, there might be as many as a dozen instructions being executed at once, at various stages of completion (super pipelining).

Jim